1. Technical Field
The present disclosure relates in general to a circuit for power management of standard cell application. In particular, the present disclosure relates to a circuit for power management of differential cascode voltage switch (DCVS) logic cells and differential cascode voltage switch with pass-gate (DCVSPG).
2. Description of the Related Art
Differential cascode voltage switch (DCVS) logic is a dual-rail CMOS circuit technique with advantages over single-rail traditional logic circuit techniques in terms of circuit delay, layout area and logic flexibility. A further advantage to DCVS circuits is the fact that they can be readily designed for a complex Boolean logic function within single gate delay using straightforward procedures based on Karnaugh maps and tabular methods. The logic function may also be synthesized.
An application entitled “Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems” is disclosed on IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997. FIG. 1A and FIG. 1B are conventional circuits of DCVS AND logic cell and DCVSPG AND logic cell, respectively.
In FIG. 1A, the DCVS circuit comprises two cross-coupled PMOS transistors p11 and p12 forming the circuit load. Below the PMOS load, four NMOS transistors n11, n12, n13, and n14 form the n-channel logic evaluation tree. Transistors n11 and n12 are turned on when the input signals A and B swing from low to high. The node QN is then discharged to the ground. The node Q floats at the transition period when the complementary input signals AN and BN swing from high to low. Both of the NMOS transistors n13 and n14 are turned off. The cross-coupled PMOS transistor p12 is turned on by the ground level at the node QN. The output node will be charged to high. Thus, the AND logic function is realized.
The DCVSPG AND circuit shown in FIG. 1B also comprises two cross-coupled PMOS transistors p21 and p22 forming the circuit load. The cross-coupled PMOS device load is the same as in FIG. 1A. With the same previous state, when both input signals A and B swing from low to high, the NMOS transistors n22 and n24 are both turned on. The node QN is then discharged into ground when the complementary signals AN and BN swing from high to low.
However, the conventional circuits described suffer standby leakage problems when the circuits are in standby mode. Standby leakage problems are serious concerns in very deep submicron technology with device size reductions, causing output state of DCVS or DCVSPG logic cells changed. FIG. 2 shows current leakage sources in a transistor 10. The transistor 10 comprises a gate 12, a source 14, a drain 16 and a well 18. Current leakage is caused by junction leakage I1, weak inversion I2, drain induced barrier lowering I3, gate induced drain leakage I4, punchthrough I5, narrow width effect I6, gate oxide tunneling I7 and hot carrier injection I8. Thus, data stored in a logic cell of a chip can be lost in standby mode because of standby leakage.
Solutions to the standby leakage problem mentioned, especially subthreshold leakage and gate leakage, generally involve increased package costs and design difficulty in handling power distribution. In addition, excessive power consumption limits the usage of very deep submicron technology due to increased processing costs as well as extra costs to handle the unexpected power. Thus, power management has become a significant and challenging issue in recent chip design.
U.S. Pat. No. 6,287,920 to Chatterjee, et al. discloses a method for forming multiple threshold voltage integrated into circuit transistors. Angled pocket type implants are formed to create asymmetric regions. The source and drain regions are connected such that multiple threshold voltage transistors are formed. Several different threshold voltage libraries must be employed to implement the multiple threshold voltage method. In addition, power saving is typically limited and often insufficient. The multiple threshold voltage method requires extra masks for different threshold voltage and power.
U.S. Pat. No. 6,664,608 to Burr, et al. discloses a back-biased MOS device. A plurality of p-wells and n-wells are formed on a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side thereof and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected p-wells. However, disadvantages of the back-biased method include the need for additional charge pump or multiple power supplies to apply extra bias to the well and/or substrate, junction or gate oxide breakdown concerns, excessive time required to charge or discharge between different modes, deep N-well process required, wasted power and design difficulty.
U.S. Pat. No. 6,667,648 to Stout, et al. discloses a voltage island communications circuit. An integrated circuit comprises a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives the first signal and converts the first signal to a second signal of the same logical value as the first signal and is referenced to the voltage of the second power supply. However, complicated design and tools are required by the voltage island method. In addition, the voltage island method cannot solve leakage problems in most active circuit blocks.
The conventional methods described comprise use multiple Vt libraries, back-biased and voltage island methods to solve power consumption problems during standby mode. However, these cannot solve the gate leakage problem without changing the normal power supply voltage, creating design problems and delays in the systems resuming normal operation.